SH7205 Datasheet, PDF (315/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
22 to 20 WRON[2:0] 000 R/W WR Assert Wait Select
These bits specify the number of wait states to be inserted
before the external data write signal (WE3 to WE0) is
asserted.
000: 0 wait states
:
111: 7 wait states
19

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
18 to 16 RDON[2:0] 000 R/W RD Assert Wait Select
These bits specify the number of wait states inserted
before the external data read signal (RD) is asserted.
000: 0 wait states
:
111: 7 wait states
15 to 11 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
10 to 8 WDOFF[2:0] 000 R/W Write Data Output Delay Cycle Select
These bits specify the number of cycles from the end of
the wait cycle (negation of the WE3 to WE0 signals) to the
negation of the external data bus during write operation.
000: 0 wait states
:
111: 7 wait states
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 283 of 1868
REJ09B0372-0100