SH7205 Datasheet, PDF (204/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.2 Interrupt Control Registers 0 (C0ICR0, C1ICR0)
C0ICR0 and C1ICR0 are 16-bit registers that set the input signal detection mode for the external
interrupt input pin NMI, and indicate the input level at the NMI pin.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NMIL -
-
-
-
-
- NMIS -
-
-
-
-
-
-
-
Initial value: *
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
15
NMIL
*
R
NMI Input Level
This bit sets the level of the signal input to the NMI pin.
The NMI pin level can be obtained by reading this bit. This
bit cannot be modified.
0: Low level is input to NMI pin.
1: High level is input to NMI pin.
14 to 9 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
NMIS
0
R/W NMI Edge Select
This bit selects whether interrupt request signals are
detected on the falling or rising edge of NMI input.
0: Interrupt request is detected on falling edge of NMI
input.
1: Interrupt request is detected on rising edge of NMI input.
Note: C0ICR0 and C1ICR0 must be the same in the value
set in this bit.
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * The initial value is either 1 when the NMI pin is high, or 0 when the NMI pin is low.
Rev. 1.00 Mar. 25, 2008 Page 172 of 1868
REJ09B0372-0100