SH7205 Datasheet, PDF (111/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.4.5 Shift Instructions
Table 2.14 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAD Rm,Rn
SHAL
SHAR
SHLD
Rn
Rn
Rm,Rn
SHLL
Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Instruction Code
0100nnnn00000100
0100nnnn00000101
0100nnnn00100100
0100nnnn00100101
0100nnnnmmmm1100
0100nnnn00100000
0100nnnn00100001
0100nnnnmmmm1101
0100nnnn00000000
0100nnnn00000001
0100nnnn00001000
0100nnnn00001001
0100nnnn00011000
0100nnnn00011001
0100nnnn00101000
0100nnnn00101001
Operation
Execu-
tion
Cycles
Compatibility
SH2,
T Bit SH2E SH4 SH-2A
T ← Rn ← MSB
1
MSB Yes Yes Yes
LSB → Rn → T
1
LSB Yes Yes Yes
T ← Rn ← T
1
MSB Yes Yes Yes
T → Rn → T
1
LSB Yes Yes Yes
When Rm ≥ 0, Rn << Rm → Rn 1

When Rm < 0, Rn >> |Rm| →
[MSB → Rn]
Yes Yes
T ← Rn ← 0
1
MSB Yes Yes Yes
MSB → Rn → T
1
LSB Yes Yes Yes
When Rm ≥ 0, Rn << Rm → Rn 1

When Rm < 0, Rn >> |Rm| →
[0 → Rn]
Yes Yes
T ← Rn ← 0
1
MSB Yes Yes Yes
0 → Rn → T
1
LSB Yes Yes Yes
Rn << 2 → Rn
1
 Yes Yes Yes
Rn >> 2 → Rn
1
 Yes Yes Yes
Rn << 8 → Rn
1
 Yes Yes Yes
Rn >> 8 → Rn
1
 Yes Yes Yes
Rn << 16 → Rn
1
 Yes Yes Yes
Rn >> 16 → Rn
1
 Yes Yes Yes
Rev. 1.00 Mar. 25, 2008 Page 79 of 1868
REJ09B0372-0100