SH7205 Datasheet, PDF (1441/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(3) Summary of Blitter Operations
The text below provides a summary of blitter operations. Table 26.9 shows allowable
combinations of operations. Chromakey processing, color gradation processing, and logical
operations cannot be performed simultaneously. Chromakey processing is allowed only during a
fill operation. Color gradation processing can be performed only during blitting. Logical
operations, blending, and resizing can be performed irrespective of blit/filling (subject to some
restrictions).
Table 26.9 Allowable Combinations of Blitter Operations
Operation
SB Path Operations (the SBSEL bits of
(the BTYPE bits
the GR_BLTMODE register)
of the
Color
Item GR_BLTMODE Chromakey Gradation Logical
No. register)
Processing Processing Operations
Blending
(the FBFA bits
of the
GR_BRD1CNT Reference
register)
Sections
1 Blitting
×
×
×
×
26.4.3 (3) (c)
2
×
×
×
O
3
×
×
O
×
−
4
×
×
O
O
−
5
×
O
×
×
26.4.3 (3) (f)
6*¹
×
O
×
O*²
7 Filling
×
×
×
×
−
8
×
×
O
×
−
9
×
×
×
O
26.4.3 (3) (b)
10
×
×
O
O
26.4.3 (3) (e)
11
O
×
×
×
26.4.3 (3) (d)
12
O
×
×
O
Notes: Resizing function: During a blitting operation, resizing can be turned on/off on each items; it
cannot be used during a filling operation.
1. The resizing function can be applied only to full resizing; it cannot be used for partial
resizing.
2. Only SA-input data is eligible for blending; blending with register-stored data cannot be
performed.
As a summary of blitter operations, the text below provides an example where target planes P1
and P2 are blended for full-plane synthesis, and the results are written back to an arbitrary memory
space PX on the SDRAM.
Rev. 1.00 Mar. 25, 2008 Page 1409 of 1868
REJ09B0372-0100