SH7205 Datasheet, PDF (441/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.15 DMA Arbitration Status Register (DMASTS)
DMASTS is used to reference the DMA transfer status of each channel. Writing to this register is
invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAS DAS DAS DAS DAS DAS DAS DAS DAS DAS DAS DAS DAS DAS
TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 DASTS0 H'0000 R
to
DASTS13
When read: DMA Arbitration Status
0: Operand transfer not in progress
1: Operand transfer in progress
These bits enable you to reference the DMA transfer status of
each channel.
• Condition for setting these bits to 1
The bit corresponding to the channel that has started
operand transfer or non-stop transfer is set to 1.
• Condition for clearing these bits to 0
When single operand transfer or non-stop transfer ends, the
bit of the corresponding channel is cleared to 0.
Note: In DMA transfer to external devices, the DMA arbitration
status bit (DASTS) may be cleared before the end of
external bus access (the last data-write operation is
already started).
17 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Note: Bits 31 to 18 correspond to channels 0 to 13.
Rev. 1.00 Mar. 25, 2008 Page 409 of 1868
REJ09B0372-0100