SH7205 Datasheet, PDF (275/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
Section 9 Cache
9.1 Features
• Capacity
Instruction cache: 8 Kbytes × 2 cores (CPU0/CPU1)
Operand cache: 8 Kbytes × 2 cores (CPU0/CPU1)
• Structure: Instructions/data separated, 4-way set associative
• Way lock function (only for operand cache): Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 128 entries/way
• Write system: Write-back/write-through selectable
• Replacement method: Least-recently-used (LRU) algorithm
9.1.1 Cache Structure
The cache separates data and instructions and uses a 4-way set associative system. It is composed
of four ways (banks), each of which is divided into an address section and a data section.
The address and data sections per way are divided into 128 entries. The data section of the entry is
called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2 Kbytes
(16 bytes × 128 entries), which makes a total of 8 Kbytes as a whole cache (four ways).
There are two caches: cache 0 is incorporated in CPU0 and cache 1 is incorporated in CPU1. The
two have the same functions.
Although the control registers for cache 0 and cache 1 are allocated to the same address, access
from CUP0 will be to cache 0 and access from CPU1 will be to cache 1.
In this section, "cache" inclusively refers to both cache 0 and cache 1.
Rev. 1.00 Mar. 25, 2008 Page 243 of 1868
REJ09B0372-0100