SH7205 Datasheet, PDF (1213/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
13
SOFR
0
R/W*² Frame Number Refresh Interrupt Status*³
Indicates the frame number refresh interrupt status.
This bit is set to 1 in the following conditions.
• When the host controller function is selected
The frame number is updated with the UACT bit
corresponding to PRT0 or PORT1 set to 1.
(detected every 1 ms)
• When the function controller function is selected
When the frame number is updated (detected
every 1 ms)
This bit is set by internal interpolation of the
frame number even when a damaged SOF
packet is received from the USB host.
0: SOF interrupt has not occurred
1: SOF interrupt has occurred
12
DVST
*¹
R/W*² Device State Transition Interrupt Status*³*⁵
When the function controller function is selected, this
module updates the DVSQ value and sets this bit to
1 on detecting a transition in the device state.
After this interrupt has occurred, clear the status
before the next device state transition takes place.
0: Device state transition interrupt has not occurred
1: Device state transition interrupt has occurred
11
CTRT
0
R/W*² Control Transfer Stage Transition Interrupt Status*³*⁶
When the function controller function is selected, this
module updates the CTSQ value and sets this bit to
1 on detecting a change in the control transfer stage.
After this interrupt has occurred, clear the status
before the next control transfer stage transition takes
place.
0: Control transfer stage transition interrupt has not
occurred
1: Control transfer stage transition interrupt has
occurred
Rev. 1.00 Mar. 25, 2008 Page 1181 of 1868
REJ09B0372-0100