SH7205 Datasheet, PDF (545/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name value R/W Description
3
TOCL
0
R/(W)*³ TOC Register Write Protection*¹
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
enabled
1: Write access to the TOCS, OLSN, and OLSP bits is
disabled
2
TOCS
0
R/W TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
1
OLSN
0
R/W Output Level Select N*²
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.28.
0
OLSP
0
R/W Output Level Select P*²
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.29.
Notes: 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
control.
2. Clearing the TOCS0 bit to 0 makes this bit setting valid.
3. After power-on reset, 1 can be written only once. After 1 has been written, 0 cannot be
written.
Table 12.28 Output Level Select Function
Bit 1
Function
Compare Match Output
OLSN Initial Output Active Level _{Up Count}
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.
Rev. 1.00 Mar. 25, 2008 Page 513 of 1868
REJ09B0372-0100