SH7205 Datasheet, PDF (180/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.5 Sleep Errors
6.5.1 Sleep Error Source
A sleep error occurs if issuance of the sleep instruction by CPU0 is detected when the sleep error
occurrence notification for CPU0 is set and the sleep error enable bit (SLPERE) of the standby
control register 1 (STBCR1) is 1. For details, see section 30, Power-Down Modes.
6.5.2 Sleep Error Exception Handling
When a sleep error occurs, sleep error exception handling starts after the bus cycle in which the
sleep error occurred ends and the execution of the current instruction is completed. The CPU
operates as follows:
1. The exception service routine start address which corresponds to the sleep error that occurred
is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
5. Clear the sleep error enable bit (SLPERE) of the standby control register 1 (STBCR1) to 0 in
the sleep error exception handling routine.
To detect a sleep error again, set the sleep error enable bit of the standby control register 1 to 1
after the corresponding sleep instruction of CPU0.
Rev. 1.00 Mar. 25, 2008 Page 148 of 1868
REJ09B0372-0100