SH7205 Datasheet, PDF (264/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
Bit
Bit Name
15
SCMFC0
14
SCMFC1
13
SCMFD0
12
SCMFD1
11 to 7 
Initial
Value
0
0
0
0
All 0
R/W Description
R/W C Bus Cycle Condition Match Flag 0
When the C bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 0 does not
match.
1: The C bus cycle condition for channel 0 matches.
R/W C Bus Cycle Condition Match Flag 1
When the C bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The C bus cycle condition for channel 1 does not
match.
1: The C bus cycle condition for channel 1 matches.
R/W I Bus Cycle Condition Match Flag 0
When the I bus cycle condition in the break conditions
set for channel 0 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 0 does not
match.
1: The I bus cycle condition for channel 0 matches.
R/W I Bus Cycle Condition Match Flag 1
When the I bus cycle condition in the break conditions
set for channel 1 is satisfied, this flag is set to 1. In
order to clear this flag, write 0 to this bit.
0: The I bus cycle condition for channel 1 does not
match.
1: The I bus cycle condition for channel 1 matches.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 232 of 1868
REJ09B0372-0100