SH7205 Datasheet, PDF (187/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.8 When Exception Sources Are Not Accepted
When an address error, sleep error, FPU exception, register bank error (overflow), or interrupt is
generated immediately after a delayed branch instruction, it is sometimes not accepted
immediately but stored instead, as shown in table 6.10. When this happens, it will be accepted
when an instruction that can accept the exception is decoded.
Table 6.10 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of
Occurrence
Address
Error
FPU
Register Bank
Sleep Error Exception Error (Overflow) Interrupt
Immediately after a Not accepted Not accepted Not
delayed branch
accepted
instruction^*
Not accepted
Not
accepted
Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 1.00 Mar. 25, 2008 Page 155 of 1868
REJ09B0372-0100