SH7205 Datasheet, PDF (1633/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Section 32 List of Registers
This section gives information on the on-chip I/O registers of this LSI in the following structure.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
• Registers are described by functional module, in order of the corresponding section numbers.
• Access to reserved addresses which are not described in this register address list is prohibited.
• When registers consist of 16 or 32 bits, the addresses of the MSBs are given assuming big
endian.
2. Register Bits
• Bit configurations of the registers are described in the same order as the Register Addresses
(by functional module, in order of the corresponding section numbers).
• Reserved bits are indicated by — in the bit name.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register States in Each Operating Mode
• Register states are described in the same order as the Register Addresses (by functional
module, in order of the corresponding section numbers).
• For the initial state of each bit, refer to the description of the register in the corresponding
section.
• The register states described are for the basic operating modes. If there is a specific reset for an
on-chip peripheral module, refer to the section on that on-chip peripheral module.
4. Notes when Writing to the On-Chip Peripheral Modules
• To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design. When the CPU writes data to an on-chip
peripheral register, the CPU executes the succeeding instruction without waiting for the
completion of writing to the register. For example, a case in which the system enters software
standby mode for power saving is described here. To make this transition, the SLEEP
instruction must be performed after setting the STBY bit in the STBCR register to 1. However,
a dummy read of the STBCR register is required before executing the SLEEP instruction. If a
dummy read is omitted, the CPU executes the SLEEP instruction before the STBY bit is set to
1, thus the system enters sleep mode not software standby mode. A dummy read of the STBCR
register is indispensable to complete writing to the STBY bit. To reflect the change made to an
on-chip peripheral register while performing the succeeding instruction, dummy-read the
register to which write instruction is applied and then execute the succeeding instruction.
Rev. 1.00 Mar. 25, 2008 Page 1601 of 1868
REJ09B0372-0100