SH7205 Datasheet, PDF (36/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Items
Interrupt controller
(INTC)
User break controller
(UBC)
Cache memory
Specification
• Inter-processor interrupts for synchronization control
• Seventeen external interrupt pins (NMI, IRQ7 to IRQ0, and PINT7 to
PINT0)
• On-chip peripheral interrupts: Priority level set for each module
• Programmable 16 priority levels
• Register bank enabling fast register saving and restoring in interrupt
processing
• Two break channels
• Addresses, data values, access modes, and data size can be set as
break conditions
• Instruction cache: 8 Kbytes × 2 cores (CPU0, CPU1)
• Operand cache: 8 Kbytes × 2 cores (CPU0, CPU1)
• 128-entry/way, 4-way set-associative, 16-byte block length
configuration each for the instruction cache and operand cache
• Write-back, write-through, LRU replacement algorithm
• Way lock function available (only for operand cache); ways 2 and 3 can
be locked
Rev. 1.00 Mar. 25, 2008 Page 4 of 1868
REJ09B0372-0100