SH7205 Datasheet, PDF (1199/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.12 Interrupt Enable Register 0 (INTENB0)
INTENB0 enables or disables various interrupts. If an interrupt for which the corresponding bit in
this register is set to 1 has occurred, an interrupt request is output to the interrupt controller.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15
VBSE
0
R/W VBUS Interrupts Enable
Enables/disables the interrupt request when VBUS
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
14
RSME
0
R/W Resume Interrupts Enable*
Enables/disables the interrupt request when RESM
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
13
SOFE
0
R/W Frame Number Update Interrupts Enable
Enables/disables the interrupt request when SOF
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
12
DVSE
0
R/W Device State Transition Interrupts Enable*
Enables/disables the interrupt request when DVST
interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 1.00 Mar. 25, 2008 Page 1167 of 1868
REJ09B0372-0100