SH7205 Datasheet, PDF (786/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• Clock synchronous mode:
N=
Pφ
× 10⁶ − 1
8 × 2^2n-1 × B
B:
Bit rate (bits/s)
N:
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 16.3.)
Table 16.3 SCSMR Settings
n
Clock Source
0
Pφ
1
Pφ/4
2
Pφ/16
3
Pφ/64
CKS[1]
0
0
1
1
SCSMR Settings
CKS[0]
0
1
0
1
The bit rate error in asynchronous mode is given by the following formula:
When baud rate generator operates in normal mode (the BGDM bit of SCEMR is 0):
Error (%) =
Pφ × 10⁶
− 1 _{× 100 (Operation on a base clock with}
(N + 1) × B × 64 × 2^2n-1
a frequency of 16 times the bit rate)
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 32 × 2^2n-1
× 100
(Operation on a base clock with
a frequency of 8 times the bit rate)
When baud rate generator operates in double speed mode (the BGDM bit of SCEMR is 1):
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 32 × 2^2n-1
× 100
(Operation on a base clock with
a frequency of 16 times the bit rate)
Error (%) =
Pφ × 10⁶
−1
(N + 1) × B × 16 × 2^2n-1
× 100
(Operation on a base clock with
a frequency of 8 times the bit rate)
Rev. 1.00 Mar. 25, 2008 Page 754 of 1868
REJ09B0372-0100