SH7205 Datasheet, PDF (142/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Multi-Core Processor
4.3.2 Exclusive Control for CPUs
(1) Using the Semaphore Registers for Exclusive Control of CPU Access to Resources
A procedure for exclusive control of resource access by the two CPUs is given below. A sample
program for this procedure is shown in figure 4.2.
1. In the initialization routine for either of the CPUs, set all of the SEMF bits in SEMR0 to
SEMR31 to 1 (this indicates that all resources are free).
2. For example, assume that SEMR0 is used for semaphore control of resource A and that CPU0
wants to use resource A. In this case, CPU0 should read the SEMF bit in SEMR0 repeatedly
until the bit is read as 1
3. CPU0 recognizes that it has read 1 from the SEMF bit in SEMR0. This clears the SEMF bit to
0.
4. CPU0 then uses resource A. While resource A is in use by CPU0, CPU1 can only read 0
(resource A is in use) from the SEMF bit of SEMR0, and thus cannot use resource A.
5. After CPU0 has finished using resource A, it sets the SEMF bit in SEMR0 to 1 (resource A is
free).
Rev. 1.00 Mar. 25, 2008 Page 110 of 1868
REJ09B0372-0100