SH7205 Datasheet, PDF (205/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.3 Interrupt Control Registers 1 (C0ICR1, C1ICR1)
C0ICR1 and C1ICR1 are 16-bit registers that specify the detection mode for external interrupt
input pins IRQ7 to IRQ0 individually: falling edge, rising edge, both edges, or low level.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
15
IRQ71S 0
14
IRQ70S 0
13
IRQ61S 0
12
IRQ60S 0
11
IRQ51S 0
10
IRQ50S 0
9
IRQ41S 0
8
IRQ40S 0
7
IRQ31S 0
6
IRQ30S 0
5
IRQ21S 0
4
IRQ20S 0
3
IRQ11S 0
2
IRQ10S 0
1
IRQ01S 0
0
IRQ00S 0
[Legend]
n = 7 to 0
R/W Description
R/W IRQ Sense Select
R/W These bits select whether interrupt signals input to pins
R/W
IRQ7 to IRQ0 are detected on a low level, falling edge,
rising edge, or both edges.
R/W _{00: Interrupt request is detected on low level of IRQn input.}
R/W _{01: Interrupt request is detected on falling edge of IRQn}
R/W
input.
R/W 10: Interrupt request is detected on rising edge of IRQn
R/W
input.
R/W
11: Interrupt request is detected on both edges of IRQn
input.
R/W _{Note: C0ICR1 and C1ICR1 must be the same in each}
R/W
value set in IRQ71S to IRQ0S.
R/W
R/W
R/W
R/W
R/W
Rev. 1.00 Mar. 25, 2008 Page 173 of 1868
REJ09B0372-0100