SH7205 Datasheet, PDF (845/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. The
SSTDR that has not been enabled must not be accessed.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7 to 0
H'00
R/W
Description
Serial transmit data
Table 17.3 Correspondence between the DATS Bit Setting and SSTDR
SSTDR
0
1
2
3
00
Valid
Invalid
Invalid
Invalid
DATS[1:0] (SSCRL[1:0])
01
10
11 (Setting Disabled)
Valid
Valid
Invalid
Valid
Valid
Invalid
Invalid
Valid
Invalid
Invalid
Valid
Invalid
Rev. 1.00 Mar. 25, 2008 Page 813 of 1868
REJ09B0372-0100