SH7205 Datasheet, PDF (1899/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

SSU timing ........................................... 1790
Stack status after exception handling
ends......................................................... 156
Stack status after interrupt exception
handling .................................................. 208
Standby control circuit............................ 115
Status register (SR)................................... 46
Synchronous serial communication
unit (SSU)............................................... 799
System control instructions....................... 81
System matrix ......................................... 950
T
T bit .......................................................... 53
TAP controller ...................................... 1595
TDO output timing ............................... 1596
Test mode settings ................................ 1001
(Potential) time master.......................... 1014
Time slave ............................................ 1015
Time trigger control (TT control) ........... 946
Time triggered transmission ................. 1010
Timestamp .............................................. 945
Timing to clear an interrupt source......... 220
Transfer clock ......................................... 816
Transfer rate............................................ 847
Trap instruction....................................... 152
TTW[1:0] (time trigger window)............ 947
Tx-trigger control field ........................... 947
Tx-trigger time (TTT) ............................. 946
Types of exception handling and
priority order ........................................... 135
U
UBC timing........................................... 1784
Unconditional branch instructions
with no delay slot ...................................... 53
USB 2.0 host/function module
(USB) .................................................... 1123
USB data bus resistor control................ 1262
USB Timing.......................................... 1807
User break controller (UBC)................... 221
User break interrupts............................... 195
User debugging interface (H-UDI) ....... 1583
Using alarm function............................... 725
Using interval timer mode....................... 695
Using watchdog timer mode ................... 693
V
Vector base register (VBR)....................... 47
W
Watchdog timer (WDT) .......................... 683
WDT timing.......................................... 1787
Rev. 1.00 Mar. 25, 2008 Page 1867 of 1868
REJ09B0372-0100