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SH7205 Datasheet, PDF (380/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
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Section 10 Bus State Controller (BSC)
Table 10.16 Case for 8-Bit External Data Bus Width (BSIZE*1 = (1, 0))
SDRAM
Type
Number
64 Mbits (× 8)
1
128 Mbits (× 8)
1
256 Mbits (× 8)
1
512 Mbits (× 8)
1
DSZ*2
001 (8 Mbytes) 010 (16 Mbytes) 011 (32 Mbytes) 100 (64 Mbytes)
DDBW*3
00 (8 bits)
00 (8 bits)
00 (8 bits)
00 (8 bits)
Row Column Row Column Row Column Row Column
Output Pin of Address Address Address Address Address Address Address Address
This LSI
Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
A[16]/ba[1]*4 addr[22]
A[15]/ba[0]*4 addr[21]
A[14]/ma[12]*4 0
A[13]/ma[11]*4 addr[20]
A[12]/ma[10]*4 addr[19]
A[11]/ma[9]*4 addr[18]
addr[22]
addr[21]
0
0
*5
0
addr[23]
addr[22]
0
addr[21]
addr[20]
addr[19]
addr[23]
addr[22]
0
0
*5
addr[9]
addr[24]
addr[23]
addr[22]
addr[21]
addr[20]
addr[19]
addr[24]
addr[23]
0
0
*5
addr[9]
addr[25]
addr[24]
addr[23]
addr[22]
addr[21]
addr[20]
addr[25]
addr[24]
0
addr[10]
*5
addr[9]
A[10]/ma[8]*4
A[9]/ma[7]*4
A[8]/ma[6]*4
A[7]/ma[5]*4
A[6]/ma[4]*4
A[5]/ma[3]*4
A[4]/ma[2]*4
A[3]/ma[1]*4
A[2]/ma[0]*4
addr[17] addr[8]
addr[16] addr[7]
addr[15] addr[6]
addr[14] addr[5]
addr[13] addr[4]
addr[12] addr[3]
addr[11] addr[2]
addr[10] addr[1]
addr[9] addr[0]
addr[18] addr[8]
addr[17] addr[7]
addr[16] addr[6]
addr[15] addr[5]
addr[14] addr[4]
addr[13] addr[3]
addr[12] addr[2]
addr[11] addr[1]
addr[10] addr[0]
addr[18] addr[8]
addr[17] addr[7]
addr[16] addr[6]
addr[15] addr[5]
addr[14] addr[4]
addr[13] addr[3]
addr[12] addr[2]
addr[11] addr[1]
addr[10] addr[0]
addr[19] addr[8]
addr[18] addr[7]
addr[17] addr[6]
addr[16] addr[5]
addr[15] addr[4]
addr[14] addr[3]
addr[13] addr[2]
addr[12] addr[1]
addr[11] addr[0]
Notes: 1. BSIZE represents the BSIZE bit in the SDCmCNT control register.
2. DSZ represents the DSZ bit in the SDRAMm address register.
3. DDBW represents the DDBW bit in the SDRAMm address register.
4. ba[1:0] and ma[12:0] represent, respectively, the SDRAM bank address and SDRAM
address.
5. When the RD, WR or PRA command is issued, this carries the pre-charge option
signal.
Rev. 1.00 Mar. 25, 2008 Page 348 of 1868
REJ09B0372-0100
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