SH7205 Datasheet, PDF (185/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.7.5 Integer Division Exceptions
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by −1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division
instruction exception that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
integer division instruction at which the exception occurred.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
6.7.6 FPU Exceptions
An FPU exception handling is generated when the V, Z, O, U or I bit in the FPU enable field
(Enable) of the floating point status register (FPSCR) is set. This indicates the occurrence of an
invalid operation exception defined by the IEEE standard 754, a division-by-zero exception,
overflow (in the case of an instruction for which this is possible), underflow (in the case of an
instruction for which this is possible), or inexact exception (in the case of an instruction for which
this is possible).
The floating-point operation instructions that may cause generation of an FPU exception handling
are FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS,
FCNVSD, and FSQRT.
An FPU exception handling is generated only when the corresponding FPU exception enable bit
(enabled) is set. When the FPU detects an exception source by a floating-point operation, FPU
operation is halted and FPU exception handling generation is reported to the CPU. When
exception handling is started, the CPU operations are as follows.
1. The start address of the exception service routine corresponding to the FPU exception handling
that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
Rev. 1.00 Mar. 25, 2008 Page 153 of 1868
REJ09B0372-0100