SH7205 Datasheet, PDF (225/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
(7) DREQER6
Bit Bit Name
7 to 4 
3
SSU TXI1
2
SSU RXI1
1
SSU TXI0
0
SSU RXI0
Initial
Value R/W
All 0 R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1: DMA transfer request is enabled and CPU interrupt
request is disabled.
(8) DREQER7
Bit Bit Name
7 to 1 
0
ADC ADI
Initial
Value R/W
All 0 R
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Transfer Enable
These bits enable or disable DMA transfer requests and
CPU interrupt requests.
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1: DMA transfer request is enabled and CPU interrupt
request is disabled.
Rev. 1.00 Mar. 25, 2008 Page 193 of 1868
REJ09B0372-0100