SH7205 Datasheet, PDF (720/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
Bit
5
4, 3
2 to 0
Bit Name
TME
Initial
Value
0

All 1
CKS[2:0] 000
R/W Description
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled
Count-up stops and WTCNT value is retained.
1: Timer enabled
R
Reserved
These bits are always read as 1. The write value
should always be 1.
R/W Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is
shown inside the parentheses in the table is the value
when the peripheral clock (Pφ) is 33 MHz.
Clock Ratio Overflow Cycle
000:1 × Pφ
(7.73 µs)
001:1/64 × Pφ
(496.5 µs)
010:1/128 × Pφ
(0.984 ms)
011:1/256 × Pφ
(1.97 ms)
100:1/512 × Pφ
(3.94 ms)
101:1/1024 × Pφ
(7.95 ms)
110:1/4096 × Pφ
(31.7 ms)
111:1/16384 × Pφ
(127.1 ms)
Note:
If bits CKS2 to CKS0 are modified when the
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
Rev. 1.00 Mar. 25, 2008 Page 688 of 1868
REJ09B0372-0100