SH7205 Datasheet, PDF (1376/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Initial
Bit
Bit name Value
R/W Description
5
INT_DHFUL 0
R
Blitter Output Buffer C Full
This bit indicates that the output buffer C for the
blitter is full.
0: Output buffer C for the blitter is not full.
1: Output buffer C for the blitter is full.
[Clearing condition]
• The hardware automatically clears the bit, when
either buffer DC1 or DC2 is empty.
[Setting condition]
• Output buffer C for the blitter is full.
4
INT_SHFUL 0
R
Blitter Input Buffer B Full
This bit indicates that the input buffer B for the blitter
is full.
0: Input buffer B for the blitter is not full.
1: Input buffer B for the blitter is full.
3 to 1 
Undefined R
[Clearing condition]
• The hardware automatically clears the bit, when
either buffer SB1 or SB2 is empty.
[Setting condition]
• Input buffer B for the blitter is full.
Reserved
The read value is undefined.
0
INT_GR
0
R
Blitter Operation Completion
This bit indicates whether the blitter operation has or
has not been completed.
0: The blitter operation is in progress or no blitter
operation has not been set up.
1: The blitter operation has been completed.
[Clearing condition]
• Writing 1 to the DIS_GR bit in GR_INTDIS.
[Setting condition]
• Completion of the blitter operation
Note: The INT_UDFL and INT_VSYC bits may be set even when the output block has not been
started. So, be sure to clear the INT_UDFL and INT_VSYC bits in the GR_INTDIS register
before starting up the output block.
Rev. 1.00 Mar. 25, 2008 Page 1344 of 1868
REJ09B0372-0100