SH7205 Datasheet, PDF (1303/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Setup
token reception
CTSQ = 000
setup stage
Setup token reception
CTSQ = 110
control transfer
sequence error
5
Error
detection
Setup token reception
Error detection and IN token reception
are valid at all stages in the box.
ACK
trans-
mission
CTSQ = 001
1 control read
data stage
OUT token
2
CTSQ = 010
control read
status stage
ACK
trans-
mission
4
CTSQ = 000
idle stage
4
ACK
transmission
1
CTSQ = 011
control write
data stage
IN token
3
CTSQ = 100
control write
status stage
ACK
reception
ACK
transmission
Note:
CTRT interrupts
(1) Setup stage completed
(2) Control read transfer status stage transition
(3) Control write transfer status stage transition
(4) Control transfer completed
(5) Control transfer sequence error
CTSQ = 101
1
control write
no data
status stage
ACK
reception
Figure 24.7 Control Transfer Stage Transitions
Rev. 1.00 Mar. 25, 2008 Page 1271 of 1868
REJ09B0372-0100