SH7205 Datasheet, PDF (1316/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
(DTCM) in the DMA mode register (DMMOD) to 10 (output of the DMA transfer end signal on
the final write cycle) whenever this function is used.
(c) Data Transferred for One Operand
In this module, the data to be transferred for each operand is selectable as one unit of data, 16
bytes, or 32 bytes by the DFACC bits in the DMA-FIFO bus-configuration registers (DnFBCFG).
• With the DFACC = 00 (access to one unit of data) setting, set the operand size for the DMAC's
method of transfer to 1 and the data size to the size selected by the MBW bits.
• With the DFACC = 01 (consecutive access to 16 bytes) setting, set the operand size for the
DMAC's method of transfer and the data size (the size selected by the MBW bits) such that the
multiple of the two is 16 bytes.
• With the DFACC = 10 (consecutive access to 32 bytes) setting, set the operand size for the
DMAC's method of transfer and the data size (the size selected by the MBW bits) such that the
multiple of the two is 32 bytes.
(d) DnFIFO Auto Clear Mode (D0FIFO/D1FIFO Port Reading Direction)
If 1 is set for the DCLRM bit in DnFIFOSEL, the module automatically clears the buffer memory
of the corresponding pipe when reading of the data from the buffer memory has been completed.
Table 24.25 shows the packet reception and buffer memory clearing processing for each of the
various settings. As shown, the buffer clear conditions depend on the value set to the BFRE bit.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a
situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA
transfers without involving software.
This function can be set only in the buffer memory reading direction.
Rev. 1.00 Mar. 25, 2008 Page 1284 of 1868
REJ09B0372-0100