SH7205 Datasheet, PDF (826/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.5 SCIF Interrupts
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 16.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. This TXI interrupt request activates the
DMA transfer or the CPU interrupt to perform data transfer. The DMA transfer or the CPU
interrupt is selectable by the DMA transfer request enable register (DREQER) of the INTC.
When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. This RXI interrupt request activates the DMA transfer
or the CPU interrupt to perform data transfer. The DMA transfer or the CPU interrupt is selectable
by the DMA transfer request enable register (DREQER) of the INTC. The RXI interrupt request
caused by the DR flag is generated only in asynchronous mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI interrupt
without requesting an RXI interrupt.
The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data
in SCFRDR.
Table 16.12 SCIF Interrupt Sources
Interrupt
Source
BRI
ERI
RXI
TXI
Description
DMAC
Activation
Interrupt initiated by break (BRK) or overrun error Not possible
(ORER)
Interrupt initiated by receive error (ER)
Not possible
Interrupt initiated by receive FIFO data full (RDF) or Possible
data ready (DR)
Interrupt initiated by transmit FIFO data empty
(TDFE)
Possible
Priority on
Reset Release
High
Low
Rev. 1.00 Mar. 25, 2008 Page 794 of 1868
REJ09B0372-0100