SH7205 Datasheet, PDF (176/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.2.4 Manual Reset
(1) Manual Reset by Means of MRES Pin
When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without
fail, the MRES pin should be kept at the low level for at least 20-tcyc. In the manual reset state,
the CPU’s internal state is initialized, but the on-chip peripheral module registers are not
initialized. In the manual reset state, manual reset exception handling starts when the MRES pin is
first driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized to 0. The BN bit in IBNR of the INTC is also initialized to 0.
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
(2) Manual Reset Initiated by WDT
Each CPU has a watchdog timer (WDT).
When either or both of the WDTs are set so that a manual reset occurs in watchdog timer mode,
and the WTCNT (or WTCNTs) of the WDT (or WDTs) overflows, this LSI enters the manual
reset state.
When manual reset exception handling is started by the WDT, the CPU operates in the same way
as when a manual reset was caused by the MRES pin.
When a manual reset is generated, the bus cycle is retained, but if a manual reset occurs during
DMAC burst transfer, manual reset exception handling will be deferred until the CPU acquires the
bus mastership. The CPU and the BN bit in IBNR of the INTC are initialized by a manual reset.
The FPU and other modules are not initialized.
Rev. 1.00 Mar. 25, 2008 Page 144 of 1868
REJ09B0372-0100