SH7205 Datasheet, PDF (1018/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition
has occurred for Mailboxes 31 to 16.
Bit[15:0]: UMSR1
0
1
Description
[Clearing Condition] Writing ‘1’ (initial value)
Unread received message is overwritten by a new message or overrun
condition
[Setting Condition]
When a new message is received before RXPR or RFPR is cleared
• UMSR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UMSR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a ‘1’ to clear.
Bit 15 to 0 — Indicate that an unread received message has been overwritten or overrun condition
has occurred for Mailboxes 15 to 0.
Bit[15:0]: UMSR0
0
1
Description
[Clearing Condition] Writing ‘1’ (initial value)
Unread received message is overwritten by a new message or overrun
condition
[Setting Condition]
When a new message is received before RXPR or RFPR is cleared
Rev. 1.00 Mar. 25, 2008 Page 986 of 1868
REJ09B0372-0100