SH7205 Datasheet, PDF (314/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.6 CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 5)
CS2WCNTn specifies the number of wait states and the number of delay cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
CSON[2:0]
-
WDON[2:0]
-
WRON[2:0]
-
RDON[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
WDOFF[2:0]
-
CSWOFF[2:0]
-
CSROFF[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
R/W: R
R
R
R
R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value
31

0
30 to 28 CSON[2:0] 000
27

0
26 to 24 WDON[2:0] 000
23

0
R/W
R
R/W
R
R/W
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
CS Assert Wait Select
These bits specify the number of wait states to be inserted
before the external chip select signal (CSn) is asserted.
000: 0 wait states
:
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
Write Data Output Wait Select
These bits specify the number of wait states to be inserted
before data is output to the external data bus.
000: 0 wait states
:
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 282 of 1868
REJ09B0372-0100