SH7205 Datasheet, PDF (183/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.7 Exceptions Triggered by Instructions
6.7.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by the trap instruction, slot illegal instructions, general illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 6.9.
Table 6.9 Types of Exceptions Triggered by Instructions
Type
Source Instruction
Comment
Trap instruction TRAPA
Slot illegal
instructions
Undefined code placed
Delayed branch instructions: JMP, JSR,
immediately after a delayed branch BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
instruction (delay slot) (including an BRAF
FPU instruction or FPU-related
CPU instruction in FPU module
standby state), instructions that
rewrite the PC, 32-bit instructions,
RESBANK instruction, DIVS
instruction, and DIVU instruction
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W
General illegal
instructions
Undefined code anywhere
besides in a delay slot (including
an FPU instruction or FPU-related
CPU instruction in FPU module
standby state)
Integer division Division by zero
exceptions
Negative maximum value ÷ (−1)
DIVU, DIVS
DIVS
FPU exceptions Instructions which cause invalid
operation exception defined by
IEEE754, division-by-zero
exception, and instructions which
may cause overflow, underflow, or
inexact exception.
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
Rev. 1.00 Mar. 25, 2008 Page 151 of 1868
REJ09B0372-0100