SH7205 Datasheet, PDF (859/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Dummy-read SSRDR
Read SSSR
No
RDRF = 1?
Yes
ORER = 1?
Yes [3]
No
[4]
Consecutive data reception? ^No
Yes
Read received data in SSRDR
RDRF automatically cleared
[1] Initial setting:
Specify the receive data format.
[2] Start reception:
When SSRDR is dummy-read with RE = 1, reception is
started.
[3], [6] Receive error processing:
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
[4] To continue single reception:
When continuing single reception, wait for time of t_SUcyc
while the RDRF flag is set to 1 and then read receive data
in SSRDR.
The next single reception starts after reading receive data
in SSRDR.
[5] To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
[5]
RE = 0
Read receive data in SSRDR
End reception
[6]
Overrun error processing
Clear the ORER bit in SSSR
End reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.8 Flowchart Example of Data Reception (SSU Mode)
Rev. 1.00 Mar. 25, 2008 Page 827 of 1868
REJ09B0372-0100