SH7205 Datasheet, PDF (1846/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
Table 33.28 Symbols for ATAPI Interface Ultrta DMA Transfer Timing
Symbol
t
2CYCTYP
t
CYC
t_2CYC
t_DS
t_DH
t
DVS
t
DVH
t
CS
t
CH
t_CVS
t
CVH
t_ZFS
t_DZFS
t
FS
t
LI
t
MLI
t_UI
t
AZ
t_ZAH
t_ZAD
t_ENV
t
RFS
t
RP
t
IORDYZ
t
ZIORDY
t_ACK
t
SS
Meaning
Typical average two-cycle time
Cycle time
Minimum two-cycle time
Data setup time (receiver)
Data hold time (receiver)
Data setup time (transmitter)
Data hold time (transmitter)
CRC data setup time (receiver)
CRC data hold time (receiver)
CRC data setup time (transmitter)
CRC data hold time (transmitter)
Setup time (from the point at which the strobe signal is driven to the first assertion
of the strobe signal) (transmitter)
Setup time (from the point at which the data signal is driven to the first assertion of
the strobe signal) (transmitter)
First strobe time
Limited interlock time
Minimum limited interlock time
Unlimited interlock time
Output release time
Output delay time
Output assert/negate time (from release timing)
Envelope time
Final strobe time
STOP assertion or DMARQ negation time
IORDY release time
Strobe driven time
DMACK# setup/hold time
Strobe stop time
Rev. 1.00 Mar. 25, 2008 Page 1814 of 1868
REJ09B0372-0100