SH7205 Datasheet, PDF (1340/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
Initial
Bit
Bit Name Value R/W Description
4
DEVINT 0
R
This bit indicates the status of the ATAPI device
interrupt IDEINT. The bit is a read-only bit. Because
the bit does not hold its status in this LSI device, it is
cleared to 0 if the IDEINT bit is 0. The ATAPI interface
treats the interrupt signal from the ATAPI device as a
level-triggered input. According to the ATAPI standard,
the ATAPI device negates IDEINT, in order to clear any
interrupt pending condition, within 400 ns after
IDEIORD# used to read from the status register is
negated.
3
TOUT
0
R/WC0 This bit indicates that an IORDY time-out was
detected. This time-out is detected if no response is
made for 150 or more enhanced bus clock cycles
(IDEIORDY pin is low). Writing 0 results in the bit being
reset.
2
ERR
0
R/WC0 This bit is set to 1 if a DMA abort is detected.
ERR = 1 if:
• The host forcibly terminates a DMA transfer.
• DTCD = 1 and a device termination occurs, leading
to ACT = 0.
Writing 0 results in the bit being reset.
1
NEND
0
R/WC0 This bit indicates that a DMA ended normally. Writing 0
results in the bit being reset.
0
ACT
0
R
This bit indicates that DMA is active. The bit is a read-
only bit. It is cleared to 0 when a DMA transfer is
completed. It is not recommended to use the bit as an
interrupt source.
Rev. 1.00 Mar. 25, 2008 Page 1308 of 1868
REJ09B0372-0100