SH7205 Datasheet, PDF (905/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
18.4.7 Noise Filter
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 18.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
D
Q
Latch
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Sampling
clock
Peripheral clock
cycle
Match
detector
NF2CYC
Figure 18.17 Block Diagram of Noise Filter
1
Internal
SCL or SDA
signal
0
Rev. 1.00 Mar. 25, 2008 Page 873 of 1868
REJ09B0372-0100