SH7205 Datasheet, PDF (211/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.9 Bank Number Registers (C0IBNR, C1IBNR)
C0IBNR and C1IBNR are 16-bit registers that enable or disable the use of register banks and
register bank overflow exception. In bits BN3 to BN0, C0IBNR and C1IBNR indicate the number
of the bank to which saving is performed next.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BE[1:0]
BOVE -
-
-
-
-
-
-
-
-
BN[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
15, 14
13
12 to 4
3 to 0
Initial
Bit Name Value R/W Description
BE[1:0] 00
R/W Register Bank Enable
These bits enable or disable the use of register banks.
00: Use of register banks is disabled for all interrupts. The
settings of C0IBCR and C1IBCR are ignored.
01: Use of register banks is enabled for all interrupts except
NMI and user break. The settings of C0IBCR and
C1IBCR are ignored.
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the settings of
C0IBCR and C1IBCR.
BOVE
0
R/W Register Bank Overflow Enable
This bit enables or disables register bank overflow exception.
0: Generation of register bank overflow exception is disabled.
1: Generation of register bank overflow exception is enabled.

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
BN[3:0] 0000 R Bank Number
These bits indicate the number of the bank to which saving is
performed next. When an interrupt is accepted and register
banks are used for the interrupt, saving is performed to the
register bank indicated by these bits, and BN is incremented
by 1. After BN is decremented by 1 due to execution of a
RESBANK (restore from register bank) instruction, restoration
from the register bank is performed.
Rev. 1.00 Mar. 25, 2008 Page 179 of 1868
REJ09B0372-0100