SH7205 Datasheet, PDF (1442/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
The areas for planes P1 and P2 are set as follows: the number of lines in the SSHIGH bits of the
GR_SABSET register, and the number of pixels in the SSWIDH bits of the GR_SABSET register.
For the PX, the number of lines is set in the DCHIGH bits of the GR_DCSET register, and the
number of pixels in the DCWIDH bits of the GR_DCSET register.
The SA and SB buffers each have a 128-byte double-buffer structure ((SA1, SA2), (SB1, SB2)).
For example, if one input is selected (i.e., SB_STEN bit = 1 and SA_STEN bit = 0 in the
GR_BLTPLY register), and if the following values are assigned: SSWIDH bits = 40 (pixels) in the
GR_SABSET register and SSHIGH bits = 4 (lines) in the GR_SABSET register, blitter operations
work as follows:
1. Transfers the first 64 pixels to SB1 (SBHF_STAT (0) = 1), followed by blitter processing and
output.
2. Transfers the next 64 pixels to SB2 (SBHF_STAT (1) = 1), followed by blitter processing and
output.
3. Transfers the remaining 32 pixels to SB1 (SBHF_STAT (0) = 1), followed by blitter
processing and output.
4. This completes the blitter operation (SB_STEN=0).
The DC buffer has a 256-byte double-buffer structure (DC1, DC2). For example, if DCWIDH bits
= 60 (pixels) in the GR_DCSET register and DCHIGH bits = 5 (lines) in the GR_DCSET register,
blitter operations work as follows:
1. Transfers the first 128 pixels to DC1 (DCHF_STAT (0) = 1), followed by a DMA transfer.
2. Transfers the next 128 pixels to DC2 (DCHF_STAT (1) = 1), followed by a DMA transfer.
3. Transfers the remaining 44 pixels to DC1 (DCHF_STAT (0) = 1), followed by a DMA
transfer.
Rev. 1.00 Mar. 25, 2008 Page 1410 of 1868
REJ09B0372-0100