SH7205 Datasheet, PDF (848/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
17.4 Operation
17.4.1 Transfer Clock
A transfer clock can be selected from among seven internal clocks and an external clock. Before
using this module, enable the SSCK pin function in the PFC. When the MSS bit in SSCRH is 1, an
internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the
clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin.
When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin.
17.4.2 Relationship of Clock Phase, Polarity, and Data
The relationship of clock phase, polarity, and transfer data depends on the combination of the
CPOS and CPHS bits in SSMR when the value of the SSUMS bit in SSCRL is 0. Figure 17.2
shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting
is valid. Transmit data change timing and receive data fetch timing in SSUMS = 1 are the same
timings shown in figure 17.2, (1) When CPHS = 0.
Setting the MLS bit in SSMR selects either MSB first or LSB first communication. When MLS =
0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB
to the LSB.
(1) When CPHS = 0
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
(2) When CPHS = 1
SCS
SSCK
(CPOS = 0)
SSCK
(CPOS = 1)
SSI, SSO
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 17.2 Relationship of Clock Phase, Polarity, and Data
Rev. 1.00 Mar. 25, 2008 Page 816 of 1868
REJ09B0372-0100