SH7205 Datasheet, PDF (348/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.5.2 Accessing SDRAM
A description is provided here of the SDRAM controller (SDRAMC) operation enable and
SDRAM bus width settings as well as operations involving SDRAM (read, write, auto-refresh,
self-refresh, initialization sequence, and mode register settings).
(1) SDRAM Access Enable/Disable and SDRAM Bus Width Settings
Enabling and disabling SDRAM access is performed by making settings in the individual
SDRAMCm control registers to enable or prohibit SDRAMC operation. SDRAM bus width
settings are also performed by means of the SDRAMCm control registers.
Even if the SDRAMC control register is set to disable SDRAMC operation, refresh operation will
still take place if self-refresh or auto-refresh operation is set as enabled.
(2) SDRAM Commands
SDRAMC controls SDRAM by issuing commands each bus cycle. These commands are defined
by combinations of RAS, CAS, WE, CKE, CS, etc.
Table 10.9 lists the commands issued by the SDRAMC.
Table 10.9 SDRAMC Commands
Mnemonic Command
SDCS RAS
DSL
Deselect
H
X
ACT
Activate row and bank
L
L
RD
Read
L
H
WR
Write
L
H
PRA
Precharge all banks
L
L
RFA
Auto-refresh
L
L
MRS
Mode register set
L
L
EMRS
Extended mode register set L
L
RFS
Self-refresh entry
L
L
RFX
Self-refresh exit
H
X
DPD
Deep-power-down
L
H
DPDX
Deep-power-down exit
X
X
[Legend]
H: High Level. L: Low Level. V: Valid. X: Don't Care.
CAS
X
H
L
L
H
L
L
L
L
X
H
X
SDWE CKE
X
X
H
H
H
H
L
H
L
H
H
H
L
H
L
H
H
H→L
X
L→H
L
H→L
X
L→H
A16 A15
(BA1) (BA0)
X
X
V
V
V
V
V
V
X
X
X
X
L
L
H
L
X
X
X
X
X
X
X
X
Rev. 1.00 Mar. 25, 2008 Page 316 of 1868
REJ09B0372-0100