SH7205 Datasheet, PDF (1233/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
3
PIPE3BEMP 0
R/W* BEMP Interrupts for PIPE3
0: Interrupt has not occurred
1: Interrupt has occurred
2
PIPE2BEMP 0
R/W* BEMP Interrupts for PIPE2
0: Interrupt has not occurred
1: Interrupt has occurred
1
PIPE1BEMP 0
R/W* BEMP Interrupts for PIPE1
0: Interrupt has not occurred
1: Interrupt has occurred
0
PIPE0BEMP 0
R/W* BEMP Interrupts for PIPE0
0: Interrupt has not occurred
1: Interrupt has occurred
Note: * Only 0 can be written to these bits.
24.3.25 Frame Number Register (FRMNUM)
FRMNUM determines the source of isochronous error notification and indicates the frame
number.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OVRN CRCE —
—
—
FRNM[10:0]
Initial value: 0
0
-
-
-
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 1.00 Mar. 25, 2008 Page 1201 of 1868
REJ09B0372-0100