SH7205 Datasheet, PDF (14/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

10.3 Area Overview................................................................................................................... 267
10.3.1 Address Map......................................................................................................... 267
10.3.2 Data Bus Width and Pin Function Setting for Individual Areas ........................... 269
10.4 Register Descriptions......................................................................................................... 270
10.4.1 CSn Control Register (CSnCNT) (n = 0 to 5)....................................................... 272
10.4.2 CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 5) ............................. 274
10.4.3 SDRAMCm Control Register (SDCmCNT) (m = 0, 1)........................................ 276
10.4.4 CSn Mode Register (CSMODn) (n = 0 to 5) ........................................................ 277
10.4.5 CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 5) ..................................... 280
10.4.6 CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 5) ..................................... 282
10.4.7 SDRAM Refresh Control Register 0 (SDRFCNT0)............................................. 285
10.4.8 SDRAM Refresh Control Register 1 (SDRFCNT1)............................................. 286
10.4.9 SDRAM Initialization Register 0 (SDIR0)........................................................... 288
10.4.10 SDRAM Initialization Register 1 (SDIR1)........................................................... 290
10.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ..................................... 291
10.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT) ........................ 292
10.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)............................................ 293
10.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ................................................ 295
10.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)............................................... 297
10.4.16 SDRAM Status Register (SDSTR) ....................................................................... 298
10.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .................. 300
10.4.18 AC Characteristics Switching Register (ACSWR) ............................................... 301
10.5 Operation ........................................................................................................................... 302
10.5.1 Accessing CS Space ............................................................................................. 302
10.5.2 Accessing SDRAM............................................................................................... 316
10.6 Connection Examples ........................................................................................................ 354
10.7 Usage Notes ....................................................................................................................... 359
10.7.1 Write Buffer.......................................................................................................... 359
10.7.2 Point for Caution at the Time of a Transition to Software Standby or
Deep Standby Mode ............................................................................................. 359
Section 11 Direct Memory Access Controller (DMAC)................................... 361
11.1 Features.............................................................................................................................. 361
11.2 Input/Output Pins............................................................................................................... 364
11.3 Register Descriptions......................................................................................................... 365
11.3.1 DMA Current Source Address Registers (DMCSADRn)..................................... 376
11.3.2 DMA Current Destination Address Registers (DMCDADRn)............................. 377
11.3.3 DMA Current Byte Count Register (DMCBCTn) ................................................ 378
11.3.4 DMA Reload Source Address Register (DMRSADRn) ....................................... 380
11.3.5 DMA Reload Destination Address Register (DMRDADRn) ............................... 381
Rev. 1.00 Mar. 25, 2008 Page xiv of xxxii