SH7205 Datasheet, PDF (373/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Multiple writes
CKIO
SDRAM command
ACT DSL WR WR WR WR PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-WR)
DWR
DPCG
(WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
DSL: Deselect command
Figure 10.33 Multiple Write Timing Example 2
Multiple writes
CKIO
SDRAM command
ACT DSL WR WR WR WR DSL PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-WR)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
DSL: Deselect command
DWR
(WR-PRA)
DPCG
(PRA-next)
Figure 10.34 Multiple Write Timing Example 3
Rev. 1.00 Mar. 25, 2008 Page 341 of 1868
REJ09B0372-0100