SH7205 Datasheet, PDF (1203/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.14 Interrupt Enable Register 2 (INTENB2)
INTENB2 enables or disables various interrupts. If an interrupt for which the corresponding bit in
this register is set to 1 has occurred, an interrupt request is output to the interrupt controller.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
BCHGE
—
DTCHE
ATT
CHE
—
—
—
—
EOFE
RRE
—
—
—
—
—
—
Initial value: -
0
-
0
0
-
-
-
-
0
-
-
-
-
-
-
R/W: R R/W R R/W R/W R
R
R
R R/W R
R
R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
14
BCHGE
0
R/W PORT1 USB Bus Change Interrupt Enable
Enables/disables the interrupt request when PORT1
BCHG interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
13

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
12
DTCHE
0
R/W PORT1 Disconnection Detection Interrupt Enable
Enables/disables the interrupt request when PORT1
DTCH interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
11
ATTCHE 0
R/W PORT1 Connection Detection Interrupt Enable
Enables/disables the interrupt request when PORT1
ATTCH interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 1.00 Mar. 25, 2008 Page 1171 of 1868
REJ09B0372-0100