SH7205 Datasheet, PDF (1176/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
3

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
2 to 0 RHST[2:0] 000
R
PORT0 Reset Handshake
These bits indicate the state of reset handshake on
PORT0. Table 24.6 lists the reset handshake
statuses of PORT0.
• When the host controller function is selected
These bits indicate 100 after 1 is written to USBRST.
If HSE has been set to 1 for PORT0, these bits
indicate 111 as soon as this module detects Chirp K
from the function device.
This module fixes the value of the RHST bits when 0
is written to USBRST for PORT0 and this module
completes SE0 driving. If 1xxxx is written to UTST
(i.e., a parameter for host function testing is set),
RHST indicates 011.
• When the function controller function is selected
If HSE has been set to 1 for PORT0, these bits
indicate 100 as soon as this module detects the USB
bus reset. Then, these bits indicate 011 as soon as
this module outputs Chirp K and detects Chirp JK
from the USB host three times. If the connection
speed is not settled at a high speed within 2.5 ms
after Chirp K output, these bits indicate 010.
If HSE has been set to 0 for PORT0, these bits
indicate 010 as soon as this module detects the USB
bus reset. A DVST interrupt is generated as soon as
this module detects the USB bus reset and then the
value of the RHST bits is settled at 010 or 011.
Note: When the function controller function is selected, set bits RWUPE, AUSBRST, ARESUME,
and AUACT to all 0s.
When the host controller function is selected, set bit WKUP to 0.
Rev. 1.00 Mar. 25, 2008 Page 1144 of 1868
REJ09B0372-0100