SH7205 Datasheet, PDF (1886/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Appendix
[Legend]
I:
Input
O: Output
H: High-level output
L:
Low-level output
Z:
Input pins retain their state, and output pins become high-impedance,.
+:
Output state is retained.
Notes: 1. Indicates the power-on reset by low-level input to the RES pin. The pin states after a
power-on reset by the H-UDI reset assert command or WDT overflow are the same as
the initial pin states at normal operation (see section 27, Pin Function Controller (PFC)).
2. Indicates the pin states that the IOKEEP bit in the deep standby cancel source flag
register (DSFR) is cleared if the chip has recovered from deep standby mode by the
input on any of pins NMI, MRES, and IRQ7 to IRQ0 (see section 30, Power-Down
Modes).
3. This LSI shifts to the power-on reset state for a certain period after the recovery from
the deep standby mode (see section 30, Power-Down Modes).
4. The week keeper and pull-up circuits included in the I/O pins are turned off.
5. When pins for the connection with a crystal resonator are not used, the input pins
(EXTAL, RTC_X1, AUDIO_X1, and USB_X1) must be fixed to low level or high level
and the output pins (XTAL, RTC_X2, AUDIO_X2, and USB_X2) must be open.
6. Depends on the setting of the CKOEN bit in the frequency control register (FRQCR) of
the CPG (see section 5, Clock Pulse Generator (CPG)).
7. Depends on the setting of the HIZ bit in the high impedance control register (HIZCR)
(see section 30, Power-Down Modes).
8. Depends on the setting of the HIZBSC bit in the high impedance control register
(HIZCR) (see section 30, Power-Down Modes).
9. Depends on the setting of the corresponding bit in the deep standby cancel source
select register (DSSSR) (see section 30, Power-Down Modes).
10. Depends on the setting of the RTCEN bit in the RTC control register (RCR2) of the RTC
(see section 15, Realtime Clock (RTC)).
11. Depends on the AXTALE bit in the standby control register (STBCR1) (see section 30,
Power-Down Modes).
12. Depend on the CS0KEEPE bit in the deep standby control register (DSCTR) (see
section 30, Power-Down Modes).
13. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
14. These are the pin states in product chip mode (ASEMD=H). See the Emulation Manual
(provisional title) for the pin states in ASE mode (ASEMD=L).
Rev. 1.00 Mar. 25, 2008 Page 1854 of 1868
REJ09B0372-0100