SH7205 Datasheet, PDF (1070/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 21 A/D Converter (ADC)
21.3.2 A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enables or disables starting of A/D conversion by external trigger input.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ADF ADIE ADST -
TRGS[3:0]
CKS[1:0]
MDS[2:0]
CH[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R/W: R/(W)* R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Only 0 can be written to clear the flag after 1 is read.
Initial
Bit
Bit Name Value R/W Description
15
ADF
0
R/(W)* A/D End Flag
Status flag indicating the end of A/D conversion.
[Clearing conditions]
• Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
• Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
• A/D conversion ends in single mode
• A/D conversion ends for the selected channels in
multi mode
• A/D conversion ends for the selected channels in
scan mode
14
ADIE
0
R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
Rev. 1.00 Mar. 25, 2008 Page 1038 of 1868
REJ09B0372-0100