SH7205 Datasheet, PDF (475/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
If a level sense is selected, the DMA request signal of the channel is masked from the start of the
last write access in a single operand transfer until two clock cycles after the single operand
transfer has ended. This ensures a sufficient length of time for negation of the DMA request
signal.
Figure 11.9 shows the DMA request signal mask period when a level sense is selected.
CKIO
DMAC state
(internal state)
DREQ0 to DREQ3
(low level sense)
DACK0 to DACK3
DMA request bit
Single operand transfer
Channel arbitration start
Read
Write
[Legend]
(DMA request signal mask period)
If the single operand transfer period is short, a single DMA request may activate
several DMAs because negation of DMA requests (DREQ0 to DREQ3) is too late.
To prevent such a problem from occurring, the DMA requests made during this period
are ignored.
: Sampling point for DMA request signal
Figure 11.9 DMA Request Signal Mask Period When a Level Sense Is Selected
Therefore, even if a channel for which a level sense is selected retains the DMA request signal
level (continues to request DMA transfer) as is after the DMA request is accepted, DMA requests
from other channels are accepted, if any, because it is judged that no DMA request is made during
the DMA request signal mask period.
For sequential operand transfer, however, the DMA request signal mask period becomes effective
only if operand transfer ends when the byte count reaches 0. If operand transfer ends when the
byte count is not 0, channel arbitration is performed without the DMA request masked. For non-
stop transfer, this mask period becomes effective if DMA transfer ends when the byte count is 0.
If DMA transfer is not continuously performed, the DMA request must be canceled within three
cycles after single operand transfer has ended.
Rev. 1.00 Mar. 25, 2008 Page 443 of 1868
REJ09B0372-0100