SH7205 Datasheet, PDF (253/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
Section 8 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design a self-monitoring debugger, enabling this LSI chip to debug
programs without using an in-circuit emulator. Instruction fetch or data read/write of CPU, data
size, data contents, address value, and stop timing in the case of instruction fetch are break
conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch
on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus),
and data access on the C bus is performed by issuing bus cycles on the memory access bus (M
bus). The UBC monitors the C bus and internal bus (I bus).
There are two UBCs: UBC0, which monitors the operation of CPU0, and UBC1, which monitors
the operation of CPU1. These UBCs are quite the same. The control registers of UBC0 and UBC1
are mapped to the same addresses, but the registers for UBC0 are accessed when access from
CPU0 is made and the registers for UBC1 are accessed when access from CPU1 is made. In this
section, UBC0 and UBC1 are collectively called UBC.
Rev. 1.00 Mar. 25, 2008 Page 221 of 1868
REJ09B0372-0100