SH7205 Datasheet, PDF (922/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
25
IIEN
0
R/W Idle Mode Interrupt Enable
0: Idle mode interrupt is disabled.
1: Idle mode interrupt is enabled.
24
—
0
R
Reserved
The read value is undefined. The write value should
always be 0.
23, 22 CHNL[1:0] 00
R/W Channels
These bits show the number of channels in each
system word.
00: Having one channel per system word
01: Having two channels per system word
10 Having three channels per system word
11: Having four channels per system word
21 to 19 DWL[2:0] 000
R/W Data Word Length
Indicates the number of bits in a data word.
000: 8 bits
001: 16 bits
010: 18 bits
011: 20 bits
100: 22 bits
101: 24 bits
110: 32 bits
111: Reserved
18 to 16 SWL[2:0] 000
R/W System Word Length
Indicates the number of bits in a system word.
000: 8 bits
001: 16 bits
010: 24 bits
011: 32 bits
100: 48 bits
101: 64 bits
110: 128 bits
111: 256 bits
Rev. 1.00 Mar. 25, 2008 Page 890 of 1868
REJ09B0372-0100