SH7205 Datasheet, PDF (1121/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
8
STERB 0
R/(W)* Status Error
Indicates the result of status read. This bit is set to 1 if
the specific bit in the bits STAT[7:0] in FLBSYCNT is
set to 1 in status read.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no status error occurs (the specific bit
in the bits STAT[7:0] in FLBSYCNT is 0.)
1: Indicates that a status error occurs
For details on the specific bit in STAT7 to STAT0 bits,
see section 23.4.7, Status Read.
7
BTOERB 0
R/(W)* R/B Timeout Error
This bit is set to 1 if an R/B timeout error occurs (the
bits RBTIMCNT[19:0] in FLBSYCNT are decremented
to 0).
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no R/B timeout error occurs
1: Indicates that an R/B timeout error occurs
6
TRREQF1 0
R/(W)* FLECFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLECFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
FLECFIFO
1: Indicates that a transfer request is issued from
FLECFIFO
5
TRREQF0 0
R/(W)* FLDTFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLDTFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
FLDTFIFO
1: Indicates that a transfer request is issued from
FLDTFIFO
Rev. 1.00 Mar. 25, 2008 Page 1089 of 1868
REJ09B0372-0100